The present invention relates to flip-flops, and more specifically to master slave flip-flops.
Flip-flops have a wide variety of uses in today""s computers and digital circuits. A flip-flop is used to generate a steady state output signal having either a high (logical one) or a low (logical zero) potential. As the uses for flip-flops increase, the desire to improve flip-flop performance and the desire to reduce power consumption has led to increased demand for high performance low power consumption flip-flops. Flip-flops are one of the most commonly used elements to implement sequential circuits, that is circuits in which the primary output relies not only on the current values of the input, but also the previous input values.
Master Slave D-flip flops (MS-DFF) are one of the most used types of flip-flops. They are used in building finite state machines, which the control logic of digital circuits are built upon. More advanced micro-architecture concepts, such as speculation, renaming, and out-of-order execution, are continuing to become more and more common. As such, the control logic portion of a microprocessor is becoming more and more important.
DFFs may also be used in holding a data value between pipeline stages in a data path. Therefore, high performance with reduced power consumption is desirable.
Conventional master slave D-flip flops triggered on the rising clock edge have two stages, a master stage 102 and a slave stage 104 as shown in FIG. 1. The stages are identical. When the clock signal is low, the first stage samples the data. At the same time, the second stage is isolated from the master stage by gate 106, and holds the previous data in latch 108. As the clock transitions to high, the master stage is isolated from the data input, and the slave stage is connected to the data input currently present in the master stage at the time the clock transitions to high. The previously sampled input data is transferred to the slave stage.
Each of the master and slave stages has a feedback loop in the form of a latch controlled by the clock signal CLK, its complement CLKiB as obtained by passing it through an inverter, and a delayed clock signal CLKi as obtained by passing it through yet another inverter. The feedback path holds the value in the slave stage when the clock is low and in the master stage when the clock is high. The FIG. 1 master slave flip-flop has a clock load of eight transistors.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flip-flop which has reduced power consumption and increased performance.
In one embodiment, a flip flop includes a master stage having a pass gate and an inverter, the pass gate connected between an external data input and the inverter, the master stage driven directly by the data input, and a slave stage having a feedback path for maintaining a data input value, the slave stage isolated from the master stage when a clock signal is low, and connectable to the master stage inverter on a rising clock signal.
In another embodiment, a flip-flop includes a master stage having a first transistor, a first inverter with its input connected to the first transistor, and a first half weak feedback path, and a slave stage having a second transistor, a second inverter with its input connected to the second transistor, and a second half weak feedback path.
In yet another embodiment, a method includes supplying a data input to a first network having a pass device and an inverter, isolating the first network from a second network until a triggering event, connecting the first network to the second network to pass a new data value to the second network, and holding a passed data value in the second network using a feedback path.
Other embodiments are described and claimed.